With the rapid advancement of electronic technology, the variety of memory types has grown significantly. Each type of memory operates with unique timing characteristics, which makes testing them a complex task. To enhance the efficiency of memory chip testing, a multi-functional test system has been developed. This paper presents a hardware design and implementation for a test system capable of handling various memory chips, including SRAM, MRAM, NOR FLASH, NAND FLASH, and EEPROM, each with different data bit widths. The system allows these memory chips to be connected to the NIOS II bus, enabling a unified platform for testing multiple types of memories.
**Design Principle**
Based on the distinct read and write timing requirements of various memory types, this design leverages the flexible programming capabilities of FPGAs to adjust the external bus timing of the NIOS II. This ensures accurate communication between the NIOS II and different memory chips. A custom bus interface called ABUS is implemented through the FPGA, allowing all memory chips to be mounted on a single platform. As shown in Table 1, the ABUS interface supports automatic identification of tested memory chips via a category input signal (CLAS), which determines the appropriate operational sequence for each chip. The following sections detail the interface connections and signal descriptions for several memory chips, with similar configurations applicable to other types.
**40-bit NAND FLASH Connection Design**
As illustrated in Figure 2-2, the 40-bit NAND FLASH is interfaced with the NIOS II through the ABUS (FPGA). This configuration fully converts the external bus timing into the specific timing required by the NAND FLASH. The 40-bit NAND FLASH consists of five 8-bit NAND FLASH chips, whose IO ports are combined to form a 40-bit interface. Control lines (NCLE, NALE, NRE, NWE) are shared among the chips, while chip selects (NCS0-NCS9) and busy signals (R/B0-R/B9) are independently derived. Table 2 provides detailed connections between the 40-bit NAND FLASH and the ABUS interface.
**8-bit NAND FLASH Connected to NIOS II**
The 8-bit NAND FLASH is a multi-chip device, with each chip's external bus and control lines (NALE, CLE, NWE, NRE) connected. Chip select and busy signals (NCS0-NCS9 and R/B0-R/B9) are individually extracted. Using FPGA logic, the read and write timing of the NIOS II can be adjusted to accurately operate the large-capacity 8-bit NAND FLASH module. This setup enables communication between the NIOS II and the ABUS, which then connects to the 8-bit NAND FLASH. As shown in Figure 2-3, Table 3 details the signal connections.
**40-bit SRAM Connected to NIOS II**
The 40-bit SRAM module is connected to the NIOS II via ABUS for correct read and write timing. During testing, only 8 bits are tested at a time, and the entire space is tested in five cycles. As shown in Figure 2-4, Table 4 describes the signal connections in detail.
**8-bit SRAM Connected to NIOS II**
The 8-bit SRAM module is connected to the NIOS II through the ABUS (FPGA) for accurate read and write operations. As shown in Figure 2-5, Table 5 outlines the signal connections.
**Hardware Circuit Design**
Testing NAND FLASH can take up to ten hours. To improve efficiency and speed, this design includes two identical and independent hardware systems, allowing up to two NAND FLASH devices to be tested simultaneously. Each system comprises a microprocessor (NIOS II), a large-capacity FPGA, and an ABUS interface. As shown in Figure 3-1, the RS232 communication interface facilitates data exchange between the test system and the host computer, supporting human-computer interaction. The power system generates various voltages to meet the power requirements of each chip.
**Processor Module Circuit**
The processor module includes the NIOS II soft core embedded in the FPGA, two-way RS232 communication, one FLASH core, and one SRAM chip. The CPU manages the system, performing read and write tests on various memory chips and communicating with the host computer. One RS232 circuit is used for communication, while another is for debugging and software updates. The FLASH stores program code and critical data, and the SRAM loads the program upon startup, providing a fast execution environment.
**FPGA-Based ABUS Interface Module**
The ABUS interface module consists of an FPGA, a configuration FLASH, and an EEPROM. It handles the interface between the NIOS II’s external bus and various memory modules. Each memory type requires specific timing logic, which is implemented via FPGA IP cores. During testing, a class signal (CLAS) identifies the memory type, enabling the correct timing logic to be activated. The FLASH configures the FPGA and protects data during power-on, while the EEPROM stores important system parameters.
**SIP Memory Test Extension Interface**
The memory test expansion interface features 120 pins arranged in two rows. The ABUS interface connects to this expansion interface, with 40 pins for bidirectional data or I/O lines, 8 pins for control signals, 16 pins for chip select outputs, 5 pins for class input signals, 16 pins for state inputs, and 27 pins for address lines. Additional pins handle power, ground, and signal indicators.
**ABUS Interface IP Core Design**
Each SIP memory corresponds to a specific ABUS interface IP core that ensures proper timing for read and write operations. These IP cores have a unified interface, connecting to the NIOS II external bus and converting its timing to match the memory chip’s requirements. When a valid CLAS signal is detected, the IP core switches to the appropriate timing logic. Table 5 lists the CLAS values for different SIP memories, guiding the design of the interface adapter board.
**8-bit SRAM/MRAM/NOR FLASH Interface IP Core Design**
As shown in Figure 4-1, the interface operations for SRAM, MRAM, and NOR FLASH are similar, and their timing aligns with the NIOS II bus. Therefore, it is sufficient to connect the relevant control and data lines in the FPGA. A chip select register distinguishes between 16 chip selects, with each accessible space being 128 MB. The chip select register address is set to (base address + 0x0FFFFFFC), with the base address at the highest point of the NIOS II external bus.
**16-bit SRAM/MRAM/NOR FLASH Interface IP Core Design**
As shown in Figure 4-2, the interface for 16-bit SRAM, MRAM, and NOR FLASH follows a similar structure. Only the chip select register needs to be designed to differentiate between 16 SIP chips. Each chip select can access 128 MB of space, with the same address mapping as the 8-bit version.
**32-bit SRAM/MRAM/NOR FLASH Interface IP Core Design**
As shown in Figure 4-3, the 32-bit interface also uses a chip select register to manage 16 SIP chips. Each chip select can access 128 MB of space, with the same address mapping applied.
**40-bit SRAM/MRAM/NOR FLASH Interface IP Core Design**
As shown in Figure 4-4, the 40-bit data width is handled by dividing the data into five 8-bit regions. An 8-bit wide bus accesses each region separately, and a bit select register within the IP core controls the switch between the 8-bit and 40-bit buses. The chip select register is located at (base address + 0x0FFFFFFC), and the bit select register is at (base address + 0x0FFFFFF8). This allows testing of up to 128M × 40 bits × 16 memory modules.
**8-bit NAND FLASH ABUS Interface IP Design**
As shown in Figure 4-5, the 8-bit NAND FLASH interface IP core selects one of the 16 chip selects using a chip select register. Its address is set to (base address + 0x0FFFFFFC). The read status register returns the busy signal from 16 NAND FLASH chips, and its address is (base address + 0x0FFFFFF8). Writing to (base address + 0x00) writes to the NAND FLASH data register, and reading from the same address performs a read operation. Writing to (base address + 0x01) writes to the command register, and writing to (base address + 0x02) writes to the address register.
**16-bit NAND FLASH ABUS Interface IP Design**
The 16-bit NAND FLASH interface IP core is designed based on the assumption that the product is a combination of multiple 16-bit NAND FLASH chips. As shown in Figure 4-6, the same addressing scheme applies, with the chip select register at (base address + 0x0FFFFFFC), the status register at (base address + 0x0FFFFFF8), and the data, command, and address registers at (base address + 0x00), (base address + 0x01), and (base address + 0x02), respectively.
**Verification and Summary**
After programming the FPGA and debugging the C code, the system was tested successfully. The serial port output correctly identified all memory chips and performed accurate read and write tests. This design offers a low-cost, simple, and flexible solution for testing various memory chips using FPGAs, FLASH, SDRAM, and RS232 circuits. With this system, users can easily expand the test functionality to meet market demands and support a broader range of memory chip testing.
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