Multi-function memory chip test system hardware design method

With the rapid development of electronic technology, the variety of memory types has increased significantly, each with its own unique timing requirements. To improve the efficiency of memory chip testing, a multi-functional memory chip test system has been developed. This paper presents a hardware design and implementation of such a system, focusing on detailed circuit design for various memory chips including SRAM, MRAM, NOR FLASH, NAND FLASH, EEPROM, and others with different data widths. The system addresses how to interface these memories with the NIOS II bus, ultimately enabling a unified platform for testing multiple memory types with varying bit widths. Each junction is carefully designed and implemented in hardware. **Design Principle** Based on the distinct read and write timing characteristics of various memory types, this design adjusts the external bus timing of the NIOS II through the flexible programming capabilities of an FPGA. This allows accurate access to the timing requirements of different memory chips. A custom bus interface called ABUS is created using the FPGA, which can accommodate all types of memory chips as shown in Table 1. Furthermore, the system automatically identifies the tested memory chips via a category input signal (CLAS), with each category corresponding to a specific operational sequence. Below are the interface connections and signal descriptions for several memory chips. Other memory types can be connected similarly, completing the test process. **40-bit NAND FLASH Connection Design** As illustrated in Figure 2-2, the 40-bit NAND FLASH is connected to the NIOS II via the ABUS (FPGA), fully converting the external bus timing to match that of the NAND FLASH. The 40-bit NAND FLASH consists of five independent 8-bit chips. Their external IO ports are combined into a 40-bit port, while control lines (NCLE, NALE, NRE, NWE) are shared. Chip selects (NCS0-NCS9) and busy signals (R/B0-R/B9) are independently derived. **8-bit NAND FLASH Connected to NIOSII** The 8-bit NAND FLASH is composed of multiple 8-bit chips, each with its own external bus and control lines (NALE, CLE, NWE, NRE). The chip select and busy signals (NCS0-NCS9 and NRB0-NRB9) are individually extracted. Using FPGA logic, the NIOS II’s bus timing can be adjusted to accurately operate the large-capacity 8-bit NAND FLASH module. This enables the connection from NIOS II to ABUS and then to the 8-bit NAND FLASH, as shown in Figure 2-3. **40-bit SRAM Connected to NIOSII** The 40-bit SRAM module is connected to the NIOS II via ABUS for correct timing read and write operations. During testing, only 8 bits are tested at a time, with all space tested in five steps, as shown in Figure 2-4. **8-bit SRAM Connected to NIOSII** The 8-bit SRAM is connected to the NIOS II via ABUS (FPGA) for correct timing read and write operations, as shown in Figure 2-5. **Hardware Circuit Design** When testing NAND FLASH, the test duration can reach up to ten hours. To improve efficiency and speed, this design features two identical and independent hardware systems, allowing up to two NAND FLASH devices to be tested simultaneously. Each system includes a microprocessor (NIOS II), a large-capacity FPGA, and a memory test expansion interface (ABUS). As shown in Figure 3-1, the RS232 communication interface facilitates data exchange between the test system and the host computer, supporting human-computer interaction. The power system generates suitable voltages to meet the power requirements of each chip. **Processor Module Circuit** The processor module includes a NIOS II soft core embedded in the FPGA, two-way RS232 communication, one FLASH core, and one SRAM chip. The CPU manages the entire system, handling read and write tests of various memory chips and communicating with the host computer for user interaction. One RS232 circuit is used for communication, while another is for debugging and software updates. The FLASH stores program code and critical data, and upon startup, the SRAM loads the FLASH program to provide a fast running environment for the CPU. **FPGA-Based ABUS Interface Module** The ABUS interface module comprises an FPGA chip, a configuration FLASH, and a data storage EEPROM. It connects the NIOS II's external bus to various memory modules. Each memory type requires specific timing logic, implemented via FPGA hardware code (IP core). During testing, each memory module provides a fixed class signal (CLAS) to identify itself. Based on this signal, the ABUS interface switches to the appropriate timing logic, enabling accurate read/write tests on the memory chip. The FLASH is configured to load the hardware program and protect FPGA data during power-on, while the EEPROM stores important system parameters. **SIP Memory Test Extension Interface** The memory test expansion interface includes two rows of double-row sockets, totaling 120 pins. The ABUS interface connects to this extension interface: 40 pins handle bidirectional data or I/O lines, 8 pins manage control signals, 16 pins handle chip select outputs, 5 pins manage class input signals, 16 pins handle state inputs, and 27 pins manage address lines. Additional pins can be assigned to power, ground, and signal indicators. **Design of ABUS Interface IP Core** Each SIP memory corresponds to a specific ABUS interface IP core for proper timing read and write operations. These IP cores have a unified interface, consisting of two fixed interfaces: one for the external bus connected to NIOS II, and the other for the ABUS interface. When the CLAS signal is valid, the ABUS interface converts the NIOS II’s external bus timing to match the corresponding memory chip. The IP core handles the conversion of read/write operations. Table 5 lists the CLAS values for different SIP memories, which must be set when designing the interface adapter board to ensure correct timing. **8-bit SRAM/MRAM/NOR FLASH Interface IP Core Design** As shown in Figure 4-1, the interface operations for SRAM, MRAM, and NOR FLASH are similar, and the NIOS II bus timing is fully compatible. Therefore, it is sufficient to connect the relevant control and data lines in the FPGA, with a chip select register to distinguish 16 chip selects. Each chip select can access 128MB of space, with the chip select register address set to (base address + 0x0FFFFFFC), where the base address is the highest address of the NIOS II external bus. **16-bit SRAM/MRAM/NOR FLASH Interface IP Core Design** As shown in Figure 4-2, the interface operations for SRAM, MRAM, and NOR FLASH are similar, and the NIOS II bus timing is fully compatible. Therefore, it is sufficient to connect the relevant control and data lines in the FPGA, with a chip select register to distinguish 16 chip selects. Each chip select can access 128MB of space, with the chip select register address set to (base address + 0x0FFFFFFC), where the base address is the highest address of the NIOS II external bus. **32-bit SRAM/MRAM/NOR FLASH Interface IP Core Design** As shown in Figure 4-3, the interface operations for SRAM, MRAM, and NOR FLASH are similar, and the NIOS II bus timing is fully compatible. Therefore, it is sufficient to connect the relevant control and data lines in the FPGA, with a chip select register to distinguish 16 chip selects. Each chip select can access 128MB of space, with the chip select register address set to (base address + 0x0FFFFFFC), where the base address is the highest address of the NIOS II external bus. **40-bit SRAM/MRAM/NOR FLASH Interface IP Core Design** As shown in Figure 4-4, the 40-bit data width is special. Here, the 40-bit data is divided into five 8-bit regions, each accessed via an 8-bit wide bus. The bit select register in the IP core is used to switch between the 8-bit and 40-bit buses. The chip select register address is (base address + 0x0FFFFFFC), and the bit select register address is (base address + 0x0FFFFFF8). Up to 128M × 40 bits × 16 slices of memory SRAM / MRAM / NOR FLASH can be tested. **8-bit NAND FLASH ABUS Interface IP Design** As shown in Figure 4-5, a chip select register is used to select one of the 16 chip selects. Its address is (base address + 0x0FFFFFFC). The read status register returns the busy signal of 16 NAND FLASH chips, with an address of (base address + 0x0FFFFFF8). Writing data to (base address + 0x00) writes to the NAND FLASH data register, while reading from the same address reads the data register. Writing to (base address + 0x01) writes to the command register, and writing to (base address + 0x02) writes to the address register. **16-bit NAND FLASH ABUS Interface IP Design** The 16-bit NAND FLASH can be combined in multiple ways, either with multiple 16-bit or 8-bit NAND FLASH chips. Assuming the 16-bit SIP NAND FLASH is a combination of multiple 16-bit chips, the IP core is designed accordingly. As shown in Figure 4-6, one of the 16 chip selects is selected via the chip select register, with the address (base address + 0x0FFFFFFC). The read status register returns the busy signal of 16 NAND FLASH chips, with an address of (base address + 0x0FFFFFF8). Writing to (base address + 0x00) writes to the data register, and reading from the same address reads the data register. Writing to (base address + 0x01) writes to the command register, and writing to (base address + 0x02) writes to the address register. **Verification and Summary** After writing the FPGA program and debugged C code to the FLASH, the FPGA is powered down and reconfigured. The serial port output can normally identify all set memory chips and perform accurate read/write function tests, achieving the design objective. This paper introduces a low-cost, simple, and flexible hardware design for a multi-memory test system, utilizing components like FPGA, FLASH, SDRAM, and RS232 circuits. With this solution, users can flexibly expand the test system according to market demands, enabling more memory chip testing.

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