Intel's "Embedded Multi-Chip Interconnect Bridging" (EMIB) technology is one of the most intriguing developments in this year’s chip design landscape. It enables Intel to connect multiple heterogeneous chips on a single substrate without overcrowding, offering a more efficient and compact solution. Recently, Intel shared some insights into how EMIB contributes to bandwidth improvements in its new Stratix 10 MX FPGA family.
The Stratix 10 MX FPGAs leverage second-generation high-bandwidth memory (HBM2) and are expected to integrate with an upcoming Intel CPU and Radeon GPU partnership. Using EMIB, Intel can mount up to four “porcelain stickers†on the same package, achieving a staggering 512GB/s of bandwidth. This approach not only enhances performance but also reduces the physical footprint compared to traditional methods.
In addition to HBM2, EMIB is used to attach four FPGA signal transceivers, such as PCIe interfaces. According to a white paper, Intel also addressed the challenges of using FPGAs with DDR4 memory in extending system-level architectures. While three-channel DDR4-3200 may support current FPGA needs at around 80Gb/s, scaling becomes increasingly difficult due to layout and complexity issues.
Even if enough I/O pins could be placed on an FPGA package, each additional memory channel would require a significant number of I/O buffers, leading to higher power consumption and making bandwidth more sensitive than energy efficiency. This is especially important in data centers where space and power constraints are tight.
Intel also mentioned that placing 10 DDR4 DIMM slots on a single PCB could theoretically achieve 256GB/s of throughput, but it would take up a large amount of space, which isn’t ideal for data center density.
Many of these limitations have driven AMD to develop HBM memory for its GPUs. Compared to GDDR5, HBM is more compact, requires less wiring, and consumes less power. However, HBM typically uses an interposer, which adds complexity and limits miniaturization.
EMIB, on the other hand, offers a more flexible solution. It allows Intel to integrate HBM2 without the need for an extra silicon layer, reducing both size and complexity. Unlike traditional interposers, EMIB uses micro-bumps instead of through-silicon vias (TSVs), making it easier to manufacture using standard flip-chip packaging techniques.
This innovation enables the Stratix 10 MX FPGA to achieve significantly higher memory bandwidth—up to 64 concurrent memory accesses, compared to just 4–6 DDR channels in existing solutions. The chip also features Intel’s HyperFlex architecture, allowing it to run at 1GHz. With further optimizations, it promises better performance and greater flexibility for application acceleration.
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