Intel's "Embedded Multi-Chip Interconnect Bridging" (EMIB) technology has emerged as a notable development in this year’s chip design landscape. This innovative approach enables Intel to connect multiple heterogeneous chips on a single substrate without overcrowding, offering a more efficient and compact solution. Recently, Intel shared insights into how EMIB contributes to significant bandwidth improvements in its new Stratix 10 MX FPGA family.
The Stratix 10 MX FPGA leverages second-generation high-bandwidth memory (HBM2) and integrates Intel CPUs and Radeon GPUs—though the latter hasn't been officially announced yet. By using EMIB, Intel can attach up to four "porcelain stickers," achieving an impressive 512GB/s of bandwidth. This level of performance is essential for handling complex computing tasks that demand high-speed data transfer.
In addition to HBM2, EMIB also allows Intel to connect four FPGA signal transceivers, such as PCIe interfaces. According to a white paper, Intel highlighted the challenges of using FPGAs with DDR4 memory to scale system-level architectures effectively. While three-channel DDR4-3200 might suffice for today’s FPGA needs at around 80 Gb/s, scaling becomes increasingly difficult due to layout and integration limitations.
As FPGA processing demands grow, it becomes impractical to add an infinite number of DDR I/O pins on a single substrate to meet bandwidth requirements. Even if enough I/Os could be placed, each additional memory module would require power-hungry I/O buffers, making bandwidth constraints more critical than energy efficiency in markets like data centers.
Intel also noted that placing 10 DDR4 DIMM slots on a single PCB could theoretically achieve 256GB/s throughput, but this would take up a large amount of space. In data centers, where density is crucial, such an approach isn’t feasible.
Many of these limitations have driven AMD to develop HBM memory for its GPUs. Compared to GDDR5, HBM takes up less space, requires fewer wires, and consumes less power. However, traditional HBM implementations use an interposer, which adds complexity and limits miniaturization.
EMIB offers a more flexible alternative. Unlike the interposer used in some GPUs, EMIB allows Intel’s Stratix 10 MX FPGAs to integrate HBM2 more seamlessly. It uses micro-bumps instead of through-silicon vias (TSVs), making the design more compact and easier to manufacture. Additionally, EMIB-integrated chips can be packaged using standard flip-chip techniques, avoiding many of the manufacturing complexities associated with TSVs.
These innovations enable the Stratix 10 MX FPGA to deliver exponential growth in memory bandwidth. It supports up to 64 concurrent memory accesses, far exceeding current FPGA solutions that typically support only 4–6 DDR channels. The chip also features Intel’s HyperFlex architecture, enabling it to run at 1GHz. With future optimizations, it promises even greater performance and flexibility for a wide range of applications.
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