The industry's call for zero defect demand for semiconductor components is growing, and semiconductor manufacturers are beginning to invest more to meet the needs of automotive users. As the number of electronic components in automobiles continues to increase, the quality of semiconductor components in modern automobiles must be strictly controlled to reduce the defect rate (DPM) per million parts, and the use of electronic components related to the return of the site and guarantees, etc. Minimize problems and reduce liability issues caused by failure of electronic components.
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The American Automotive Electronics Council's AEC-Q001 specification recommends a common method that uses Part Average Testing (PAT) to remove anomalous parts from the total part, thus improving component quality and quality at the supplier stage. reliability. For a particular wafer, lot number, or part group to be tested, the PAT method can indicate a test result with a total average value falling outside of 6Ïƒ. Any test result that exceeds the 6Ïƒ limit value of a particular component is considered unqualified and from the part. Excluding the total, parts that do not meet the PAT limit cannot be shipped to the customer, which improves the quality and reliability of the components.
User requirements for these specifications have made competition among suppliers even more intense. There is a lot of pressure to improve reliability and reduce defect rates, especially for many of the most important safety functions currently controlled by semiconductors, such as brakes, traction control, power and active stability control systems. Suppliers must improve the quality of parts that have already been shipped, and minimize the impact of these specifications on their yield. As manufacturing costs continue to fall and test costs remain relatively constant, test costs are increasingly increasing in manufacturing costs, and component profit margins continue to shrink. Since most of the yields are not sufficient, suppliers must thoroughly evaluate their testing procedures in order to find alternative test methods and experiment from alternative methods until the best method is found.
Without sophisticated analytical and simulation tools, suppliers will apply them without fully understanding the impact of these specifications on the supply chain. To make matters worse, if blind tests are applied and important tests are missed, the results are guaranteed even if the components are tested and the same DPM rate is used to test the shipments. Righteous, and reliability will be reduced.
Some vendors seem to think that PAT testing in wafer probing is sufficient, but studies have shown that there are many problems with this approach. The use of PAT in wafer probing is the first quality level, but in the remaining downstream manufacturing process, the variable due to numerous variables can cause more PAT outliers during package testing. If suppliers want to introduce high-quality parts, they must perform PAT testing during both wafer probing and final testing, and their customers should promote the application of this method.
The method used in real-time PAT and post-statistical PAT processing is to analyze the latest data via a number of batch processes and establish static PAT limits for each test of interest. The average of these limits is calculated to be +/- 6Ïƒ and is typically integrated into the test procedure as the upper specification limit (USL) and the lower specification limit (LSL). Static PAT limit values â€‹â€‹must be reviewed and updated at least every six months.
The preferred method is to calculate the dynamic PAT limit for each batch or wafer. The dynamic PAT limit value is usually more stringent than the static PAT limit value and any outliers that are not within the normal distribution are cleared. The most important difference is that the dynamic PAT limit is calculated on a wafer or batch basis, so the limit value will vary continuously depending on the material properties used for the wafer or batch. The dynamic PAT limit value is calculated as the mean +/- (n*Ïƒ) or median +/- (N* toughness Ïƒ) and cannot be less than the LSL specified in the test procedure or greater than USL.
The calculated PAT limit value must be taken as the lower PAT limit (LPL) and the higher PAT limit (UPL) shown in FIG. Any value that exceeds the dynamic PAT limit and is between the LSL and USL limits is considered an outlier. These outliers are usually named faults and are loaded into a specific outlier software and hardware box. Tracking the PAT limits calculated for a particular wafer or batch and the amount of anomaly detected by each test is important for later traceability. There are two main methods for implementing PAT: real-time PAT and post-statistical processing (SPP). Suppliers must be aware of whether it is more meaningful to use two different methods in probing and final testing, or whether to use only one solution.
The real-time PAT makes a sorting decision when the part is tested, based on the calculation of the dynamic PAT limit, without affecting the test time. This requires a dynamic real-time engine capable of handling complex data streams for monitoring and sampling. Again, this process requires a robust statistical engine that captures test data and performs the necessary calculations to generate new limit values, send new limit values â€‹â€‹and sorting information to the test program, and monitor the entire process. To ensure stability and controllability. Suppliers need to process probes and final tests in real time and process baseline outliers.
The statistical post-processing method will produce the same final test result. After a batch is completed, the component test is statistically processed and a sorting decision is made. However, because the sorting decision is made after the batch, the post-processing can only be used for wafer probing because the test and sorting results are related to the particular component for re-sorting. In package testing, once a component is packaged, there is no way to track or sequence it, so it is not possible to link test and sort results to specific components. SPP also requires data logging of full test results to make decisions, an increasing IT infrastructure needs (a lot of time) and a significant slowdown in test time. Since the results are post-processed, the SPP processes the baseline outliers in a batch as part of the component as a whole.
Both methods require powerful operations when processing tests and sorting results, just like regional PAT and other failure modes. An example of a regional PAT is that a qualified chip in a wafer is surrounded by multiple faulty chips. Research shows that this qualified component is likely to fail prematurely, and efforts should be made to reduce DPM in automotive components. Most suppliers must find this qualified component.
The implementation of real-time testing assumes that at the moment we are manufacturing power management components for automobiles. We load historical test data into analytical tools and perform in-depth analysis of component parameter data to find out which test is a good candidate for PAT. Tests have advantages and disadvantages, some tests are more suitable for PAT, and some tests are more important for functional testing of components. If you select all the tests for the component, the yield will be unacceptable.
The problem with some tests is that the data is not stable enough to be measured according to the PAT standard. The cause of this variability may be inherent to the component itself, or it may be caused by the testing process (eg, an instrument in an automated measuring device cannot produce accurate measurements), or it may be imported by the packaging process. The test just does not have statistical control and cannot be measured.
The baseline is used to set dynamic PAT limits for a particular wafer or batch. For example, on a wafer containing 1,000 chips, the baseline of 100 typical chips is the most appropriate statistical sample of the wafer.
Once the baseline is reached, several important tasks need to be performed before the dynamic PAT limit is applied to the real-time environment. A normal check is performed for each selected test. If the data is normally distributed, the standard deviation is calculated using the 'standard' method; however, if the data distribution is not normal, the 'strength' method is used to calculate the standard deviation.
The dynamic PAT limit value for each selected test must be calculated and stored in memory for subsequent testing. The original LSL and USL remain unchanged and are used to detect test failures according to the initial test procedure. Calculate the outliers of the selected test baseline. In the probing, the XY coordinates are saved for processing after the wafer is finished. In the package test, the baseline components are sorted into the baseline box. If an outlier in the baseline is detected, then these components are identified for retesting.
Once the baseline is reached, a dynamic PAT limit check is performed for each selected test and each component is boxed in real time. Components that do not meet the PAT limit fall into a unique 'outlier' software or hardware box that identifies them as PAT outliers for later testing.
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