1.Virtex6 GTX Transceiver Introduction of Virtex6 FPGA Xilinx in, GTX as a low power consumption gigabit transceivers, flexible configuration, powerful, and work closely with other logic resources within the FPGA, can be used to achieve a variety of high-speed interface (such as XAUI, PCIE, etc.). In the V6 series of FPGAs, the GTX operating bandwidth ranges from 600 Mb/s to 6.6 Gb/s, supports bidirectional transmission and transmission, and is independent of transmission and reception. GTX receiving and transmitting directions are composed of PMA and PCS. PCS provides rich physical coding layer features such as 8b/10b encoding and clock calibration. PMA is an analog circuit that provides high-performance serial interface features such as Pre-emphasis, balance and other functions. GTX also provides a dynamic reconfiguration interface for dynamically modifying the GTX configuration.
2. GTX Clock and Layout In the VirTIx6 FPGA, GTX is organized in Quad units. Each Quad contains 4 GTXs and 2 pairs of differential clock inputs. When multiple GTXs of the entire chip are used, it is necessary to properly distribute GTX and clock input. The clock from a Quad input can only provide a reference clock to an adjacent Quad. Downward, it can only provide a reference clock input to an adjacent Quad. It can only drive up to three Quads. When the whole chip has multiple GTXs. When using the same reference clock input, a reasonable distributed clock input can save the number of clocks required, as well as provide redundancy for the clock.
Therefore, the basic principle is that several GTXs of the same physical interface are put together, and the same reference clock is used as the clock input; if the GTX of different physical interfaces is within the driving coverage of the same reference clock, the same reference clock can be used. enter. If there are conditions, you can do clock backup; when a clock can cover more GTX, considering the uncertainty of the clock drive capability, there is no need to use more margins (one clock drive) 12 GTX). In addition, in GTP of V5, when multiple GTPs share the same reference clock input, it is required that each GTP is used in the clock chain of this input clock (even if it is not needed, it is instantiated), and the same one is not allowed to be shared. There is an unused GTP in the middle of the two GTPs of the reference clock.
3. Pre-emphasis and equalization When the GTX transceiver has poor signal quality, data loss, transmission error, etc., in order to improve the signal quality, the GTX pre-emphasis, equalization, output amplitude value, and adjustment sampling can be adjusted. The location of the point to optimize the communication quality of the GTX channel. On high-speed serial interfaces, high-frequency component attenuation is more severe than low-frequency components, resulting in signal distortion. Therefore, the pre-emphasis value and the output amplitude can be adjusted in the data transmission direction to improve the signal quality. The pre-emphasis is used to increase the intensity of the high-frequency components in the signal. The value of the pre-emphasis is set by the parameter TXPREEMPHASIS[3:0]. Adjusting the amplitude is used to increase the overall strength of the signal, which is set by the parameter TXDIFFCTRL[3:0]. The value of the equalization can be adjusted in the data receiving direction, and the position of the sampling point in the sampling window can also be adjusted. The equalization is used to compensate the high-frequency components in the received signal, so that the received signal is restored to its original state. The equalization value is determined by the parameter RXEQMIX[2:0]. The sampling point setting can be selected in the eyes of the sampling window to make the sampling more stable. For the values â€‹â€‹of the above parameters and the meaning of each value, please refer to the Virtex-6 FPGA GTX Transceivers User Guide (UG336).
4. GTX debugging means Virtex6 GTX provides four different loopbacks, namely, near-end PCS loopback, near-end PMA loopback, remote PCS loopback, and far-end PMA loopback, which can be used for positioning problems in GTX. Which part of it. At the same time, by observing the PLL clock lock signal of the GTX output, it is possible to analyze whether the problem is related to the clock. Xilinx provides a series of GTX Transceiver debugging tools and tools. The most useful is to use Chipscope for IBERT bitstream bit error rate testing (ie PRBS, pseudo-random binary sequence bit error rate test). The details of the IBERT (PRBS) test will be introduced in another blog post.
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